| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| rst_controller |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| irq_mapper |
3 |
31 |
2 |
31 |
32 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_mux_001|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_mux_001|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_mux_001 |
199 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_mux|arb|adder |
16 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_mux|arb |
8 |
0 |
4 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_mux |
395 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_demux_003 |
101 |
1 |
2 |
1 |
99 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_demux_002 |
101 |
1 |
2 |
1 |
99 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_demux_001 |
102 |
4 |
2 |
4 |
197 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|rsp_demux |
102 |
4 |
2 |
4 |
197 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_mux_003 |
101 |
0 |
2 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_mux_002 |
101 |
0 |
2 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_mux_001 |
199 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_mux |
199 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_demux_001 |
102 |
4 |
2 |
4 |
197 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|cmd_demux |
104 |
16 |
2 |
16 |
393 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_005|the_default_decode |
0 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_005 |
97 |
0 |
2 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_004|the_default_decode |
0 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_004 |
97 |
0 |
2 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_003|the_default_decode |
0 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_003 |
97 |
0 |
2 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_002|the_default_decode |
0 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_002 |
97 |
0 |
2 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_001|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router_001 |
97 |
0 |
4 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|router |
97 |
0 |
4 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|pio_0_s1_agent_rsp_fifo |
137 |
39 |
0 |
39 |
96 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|pio_0_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|pio_0_s1_agent |
271 |
39 |
41 |
39 |
287 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|timer_0_s1_agent_rsp_fifo |
137 |
39 |
0 |
39 |
96 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|timer_0_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|timer_0_s1_agent |
271 |
39 |
41 |
39 |
287 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo |
137 |
39 |
0 |
39 |
96 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|onchip_memory2_0_s1_agent |
271 |
39 |
41 |
39 |
287 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent_rsp_fifo |
137 |
39 |
0 |
39 |
96 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent |
271 |
39 |
41 |
39 |
287 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|nios2_gen2_0_instruction_master_agent |
161 |
35 |
67 |
35 |
129 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|nios2_gen2_0_data_master_agent |
161 |
35 |
67 |
35 |
129 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|pio_0_s1_translator |
100 |
6 |
18 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|timer_0_s1_translator |
84 |
22 |
33 |
22 |
55 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|onchip_memory2_0_s1_translator |
100 |
7 |
4 |
7 |
86 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|nios2_gen2_0_debug_mem_slave_translator |
100 |
5 |
8 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|nios2_gen2_0_instruction_master_translator |
101 |
51 |
0 |
51 |
93 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|nios2_gen2_0_data_master_translator |
101 |
12 |
0 |
12 |
93 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0 |
189 |
0 |
0 |
0 |
223 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| timer_0 |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pio_0 |
38 |
28 |
28 |
28 |
36 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
| onchip_memory2_0|the_altsyncram|auto_generated |
52 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| onchip_memory2_0 |
55 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper|the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk |
43 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper|the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper |
123 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem |
92 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg |
48 |
0 |
29 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im |
54 |
38 |
51 |
38 |
47 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib |
0 |
36 |
0 |
36 |
36 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo |
115 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace |
102 |
0 |
91 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace |
24 |
54 |
24 |
54 |
54 |
54 |
54 |
54 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk |
87 |
0 |
0 |
0 |
91 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk |
53 |
5 |
50 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break |
51 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci |
154 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|NIOS_LED_nios2_gen2_0_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|NIOS_LED_nios2_gen2_0_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|NIOS_LED_nios2_gen2_0_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|NIOS_LED_nios2_gen2_0_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu|the_NIOS_LED_nios2_gen2_0_cpu_test_bench |
285 |
3 |
251 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0|cpu |
149 |
1 |
31 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| nios2_gen2_0 |
149 |
1 |
0 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |