
NIOS_LED.elf:     file format elf32-littlenios2
NIOS_LED.elf
architecture: nios2:r1, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00008180

Program Header:
    LOAD off    0x00001000 vaddr 0x00008000 paddr 0x00008000 align 2**12
         filesz 0x00000020 memsz 0x00000020 flags r-x
    LOAD off    0x00001020 vaddr 0x00008020 paddr 0x00008020 align 2**12
         filesz 0x000004c4 memsz 0x000004c4 flags r-x
    LOAD off    0x000014e4 vaddr 0x000084e4 paddr 0x000084e8 align 2**12
         filesz 0x00000004 memsz 0x00000004 flags rw-
    LOAD off    0x000014ec vaddr 0x000084ec paddr 0x000084ec align 2**12
         filesz 0x00000000 memsz 0x00000118 flags rw-

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .entry        00000020  00008000  00008000  00001000  2**5
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .exceptions   00000160  00008020  00008020  00001020  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .text         00000364  00008180  00008180  00001180  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .rodata       00000000  000084e4  000084ec  000014e8  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  4 .rwdata       00000004  000084e4  000084e8  000014e4  2**2
                  CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
  5 .bss          00000118  000084ec  000084ec  000014ec  2**2
                  ALLOC, SMALL_DATA
  6 .onchip_memory2_0 00000000  00008604  00008604  000014e8  2**0
                  CONTENTS
  7 .comment      00000023  00000000  00000000  000014e8  2**0
                  CONTENTS, READONLY
  8 .debug_aranges 00000218  00000000  00000000  00001510  2**3
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_info   00001250  00000000  00000000  00001728  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 000009e9  00000000  00000000  00002978  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_line   000008d7  00000000  00000000  00003361  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_frame  00000214  00000000  00000000  00003c38  2**2
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_str    00000a09  00000000  00000000  00003e4c  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_loc    000003fb  00000000  00000000  00004855  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_alt_sim_info 00000010  00000000  00000000  00004c50  2**2
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_ranges 00000100  00000000  00000000  00004c60  2**3
                  CONTENTS, READONLY, DEBUGGING
 17 .thread_model 00000003  00000000  00000000  00005ca5  2**0
                  CONTENTS, READONLY
 18 .cpu          0000000c  00000000  00000000  00005ca8  2**0
                  CONTENTS, READONLY
 19 .qsys         00000001  00000000  00000000  00005cb4  2**0
                  CONTENTS, READONLY
 20 .simulation_enabled 00000001  00000000  00000000  00005cb5  2**0
                  CONTENTS, READONLY
 21 .stderr_dev   00000004  00000000  00000000  00005cb6  2**0
                  CONTENTS, READONLY
 22 .stdin_dev    00000004  00000000  00000000  00005cba  2**0
                  CONTENTS, READONLY
 23 .stdout_dev   00000004  00000000  00000000  00005cbe  2**0
                  CONTENTS, READONLY
 24 .sopc_system_name 00000008  00000000  00000000  00005cc2  2**0
                  CONTENTS, READONLY
 25 .quartus_project_dir 00000012  00000000  00000000  00005cca  2**0
                  CONTENTS, READONLY
 26 .sopcinfo     00032ec7  00000000  00000000  00005cdc  2**0
                  CONTENTS, READONLY
SYMBOL TABLE:
00008000 l    d  .entry	00000000 .entry
00008020 l    d  .exceptions	00000000 .exceptions
00008180 l    d  .text	00000000 .text
000084e4 l    d  .rodata	00000000 .rodata
000084e4 l    d  .rwdata	00000000 .rwdata
000084ec l    d  .bss	00000000 .bss
00008604 l    d  .onchip_memory2_0	00000000 .onchip_memory2_0
00000000 l    d  .comment	00000000 .comment
00000000 l    d  .debug_aranges	00000000 .debug_aranges
00000000 l    d  .debug_info	00000000 .debug_info
00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
00000000 l    d  .debug_line	00000000 .debug_line
00000000 l    d  .debug_frame	00000000 .debug_frame
00000000 l    d  .debug_str	00000000 .debug_str
00000000 l    d  .debug_loc	00000000 .debug_loc
00000000 l    d  .debug_alt_sim_info	00000000 .debug_alt_sim_info
00000000 l    d  .debug_ranges	00000000 .debug_ranges
00000000 l    df *ABS*	00000000 ../NIOS_LED_bsp//obj/HAL/src/crt0.o
000081b8 l       .text	00000000 alt_after_alt_main
00000000 l    df *ABS*	00000000 alt_irq_handler.c
00000000 l    df *ABS*	00000000 alt_instruction_exception_entry.c
00000000 l    df *ABS*	00000000 hello_world_small.c
000081bc l     F .text	0000002c irr
00000000 l    df *ABS*	00000000 alt_iic.c
00000000 l    df *ABS*	00000000 alt_iic_isr_register.c
00000000 l    df *ABS*	00000000 alt_irq_vars.c
00000000 l    df *ABS*	00000000 alt_load.c
00000000 l    df *ABS*	00000000 alt_main.c
00000000 l    df *ABS*	00000000 alt_sys_init.c
00000000 l    df *ABS*	00000000 alt_dcache_flush_all.c
00000000 l    df *ABS*	00000000 alt_icache_flush_all.c
00000000 l    df *ABS*	00000000 altera_nios2_gen2_irq.c
00008500 g     O .bss	00000004 alt_instruction_exception_handler
00008410 g     F .text	0000002c alt_main
00008504 g     O .bss	00000100 alt_irq
000084e8 g       *ABS*	00000000 __flash_rwdata_start
000084dc g     F .text	00000008 altera_nios2_gen2_irq_init
00008000 g     F .entry	0000000c __reset
00008020 g       *ABS*	00000000 __flash_exceptions_start
000084f8 g     O .bss	00000004 alt_argv
000104e4 g       *ABS*	00000000 _gp
00008468 g     F .text	00000074 alt_exception_cause_generated_bad_addr
00008000 g       *ABS*	00000000 __alt_mem_onchip_memory2_0
00008604 g       *ABS*	00000000 __bss_end
000082c8 g     F .text	00000068 alt_iic_isr_register
000082b0 g     F .text	00000018 alt_ic_irq_enabled
000084f0 g     O .bss	00000004 alt_irq_active
000080fc g     F .exceptions	00000060 alt_irq_handler
00008460 g     F .text	00000004 alt_dcache_flush_all
000084e8 g       *ABS*	00000000 __ram_rwdata_end
000084e4 g       *ABS*	00000000 __ram_rodata_end
00008604 g       *ABS*	00000000 end
0000815c g     F .exceptions	00000024 alt_instruction_exception_entry
00010000 g       *ABS*	00000000 __alt_stack_pointer
00008180 g     F .text	0000003c _start
0000845c g     F .text	00000004 alt_sys_init
000084e4 g       *ABS*	00000000 __ram_rwdata_start
000084e4 g       *ABS*	00000000 __ram_rodata_start
00008604 g       *ABS*	00000000 __alt_stack_base
000084ec g     O .bss	00000004 counter
000084ec g       *ABS*	00000000 __bss_start
000081e8 g     F .text	00000044 main
000084f4 g     O .bss	00000004 alt_envp
000084e4 g       *ABS*	00000000 __flash_rodata_start
0000843c g     F .text	00000020 alt_irq_init
000084fc g     O .bss	00000004 alt_argc
00008020 g       .exceptions	00000000 alt_irq_entry
00008020 g       *ABS*	00000000 __ram_exceptions_start
0000822c g     F .text	00000004 alt_ic_isr_register
000084e8 g       *ABS*	00000000 _edata
00008604 g       *ABS*	00000000 _end
00008180 g       *ABS*	00000000 __ram_exceptions_end
00008270 g     F .text	00000040 alt_ic_irq_disable
00010000 g       *ABS*	00000000 __alt_data_end
00008020 g     F .exceptions	00000000 alt_exception
0000800c g       .entry	00000000 _exit
00008464 g     F .text	00000004 alt_icache_flush_all
000084e4 g     O .rwdata	00000004 alt_priority_mask
00008230 g     F .text	00000040 alt_ic_irq_enable
00008330 g     F .text	000000e0 alt_load



Disassembly of section .entry:

00008000 <__reset>:
 * Jump to the _start entry point in the .text section if reset code
 * is allowed or if optimizing for RTL simulation.
 */
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
    /* Jump to the _start entry point in the .text section. */
    movhi r1, %hi(_start)
    8000:	00400034 	movhi	at,0
    ori r1, r1, %lo(_start)
    8004:	08606014 	ori	at,at,33152
    jmp r1
    8008:	0800683a 	jmp	at

0000800c <_exit>:
	...

Disassembly of section .exceptions:

00008020 <alt_exception>:

#else /* ALT_EXCEPTION_STACK disabled */
        /* 
         * Reserve space on normal stack for registers about to be pushed.
         */
        addi  sp, sp, -76
    8020:	deffed04 	addi	sp,sp,-76
         * documentation for details).
         *
         * Leave a gap in the stack frame at 4(sp) for the muldiv handler to
         * store zero into.
         */
        stw   ra,  0(sp)
    8024:	dfc00015 	stw	ra,0(sp)
        stw   r1,   8(sp)
    8028:	d8400215 	stw	at,8(sp)
        stw   r2,  12(sp)
    802c:	d8800315 	stw	r2,12(sp)
        stw   r3,  16(sp)
    8030:	d8c00415 	stw	r3,16(sp)
        stw   r4,  20(sp)
    8034:	d9000515 	stw	r4,20(sp)
        stw   r5,  24(sp)
    8038:	d9400615 	stw	r5,24(sp)
        stw   r6,  28(sp)
    803c:	d9800715 	stw	r6,28(sp)
        stw   r7,  32(sp)
    8040:	d9c00815 	stw	r7,32(sp)
        rdctl r5, estatus   /* Read early to avoid usage stall */
    8044:	000b307a 	rdctl	r5,estatus
        stw   r8,  36(sp)
    8048:	da000915 	stw	r8,36(sp)
        stw   r9,  40(sp)
    804c:	da400a15 	stw	r9,40(sp)
        stw   r10, 44(sp)
    8050:	da800b15 	stw	r10,44(sp)
        stw   r11, 48(sp)
    8054:	dac00c15 	stw	r11,48(sp)
        stw   r12, 52(sp)
    8058:	db000d15 	stw	r12,52(sp)
        stw   r13, 56(sp)
    805c:	db400e15 	stw	r13,56(sp)
        stw   r14, 60(sp)
    8060:	db800f15 	stw	r14,60(sp)
        stw   r15, 64(sp)
    8064:	dbc01015 	stw	r15,64(sp)
        /*
         * ea-4 contains the address of the instruction being executed
         * when the exception occured. For interrupt exceptions, we will
         * will be re-issue the isntruction. Store it in 72(sp)
         */
        stw   r5,  68(sp)  /* estatus */
    8068:	d9401115 	stw	r5,68(sp)
        addi  r15, ea, -4  /* instruction that caused exception */
    806c:	ebffff04 	addi	r15,ea,-4
        stw   r15,  72(sp)
    8070:	dbc01215 	stw	r15,72(sp)
#else
        /*
         * Test to see if the exception was a software exception or caused 
         * by an external interrupt, and vector accordingly.
         */
        rdctl r4, ipending
    8074:	0009313a 	rdctl	r4,ipending
        andi  r2, r5, 1
    8078:	2880004c 	andi	r2,r5,1
        beq   r2, zero, .Lnot_irq
    807c:	10000326 	beq	r2,zero,808c <alt_exception+0x6c>
        beq   r4, zero, .Lnot_irq
    8080:	20000226 	beq	r4,zero,808c <alt_exception+0x6c>
        /*
         * Now that all necessary registers have been preserved, call 
         * alt_irq_handler() to process the interrupts.
         */

        call alt_irq_handler
    8084:	00080fc0 	call	80fc <alt_irq_handler>

        .section .exceptions.irqreturn, "xa"

        br    .Lexception_exit
    8088:	00000706 	br	80a8 <alt_exception+0x88>
         * upon completion, so we write ea (address of instruction *after*
         * the one where the exception occured) into 72(sp). The actual
         * instruction that caused the exception is written in r2, which these
         * handlers will utilize.
         */
        stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
    808c:	df401215 	stw	ea,72(sp)
.Lunknown_16bit:
        addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */
        stw r4, 72(sp)

#else /* CDX is not Enabled and all instructions are 32bits */
        ldw r2, -4(ea) /* Instruction value that caused exception */
    8090:	e8bfff17 	ldw	r2,-4(ea)
         * debugger is present) or go into an infinite loop since the
         * handling behavior is undefined; in that case we will not return here.
         */

        /* Load exception-causing address as first argument (r4) */
        addi   r4, ea, -4
    8094:	e93fff04 	addi	r4,ea,-4

        /* Call the instruction-exception entry */
        call   alt_instruction_exception_entry
    8098:	000815c0 	call	815c <alt_instruction_exception_entry>
         * instruction
         *
         * Return code was 0: Skip. The instruction after the exception is
         * already stored in 72(sp).
         */
        bne   r2, r0, .Lexception_exit
    809c:	1000021e 	bne	r2,zero,80a8 <alt_exception+0x88>

        /*
         * Otherwise, modify 72(sp) to re-issue the instruction that caused the
         * exception.
         */
        addi  r15, ea, -4  /* instruction that caused exception */
    80a0:	ebffff04 	addi	r15,ea,-4
        stw   r15,  72(sp)
    80a4:	dbc01215 	stw	r15,72(sp)
        /* 
         * Restore the saved registers, so that all general purpose registers 
         * have been restored to their state at the time the interrupt occured.
         */

        ldw   r5,  68(sp)
    80a8:	d9401117 	ldw	r5,68(sp)
        ldw   ea,  72(sp)  /* This becomes the PC once eret is executed */
    80ac:	df401217 	ldw	ea,72(sp)
        ldw   ra,   0(sp)
    80b0:	dfc00017 	ldw	ra,0(sp)

        wrctl estatus, r5
    80b4:	2801707a 	wrctl	estatus,r5

        ldw   r1,   8(sp)
    80b8:	d8400217 	ldw	at,8(sp)
        ldw   r2,  12(sp)
    80bc:	d8800317 	ldw	r2,12(sp)
        ldw   r3,  16(sp)
    80c0:	d8c00417 	ldw	r3,16(sp)
        ldw   r4,  20(sp)
    80c4:	d9000517 	ldw	r4,20(sp)
        ldw   r5,  24(sp)
    80c8:	d9400617 	ldw	r5,24(sp)
        ldw   r6,  28(sp)
    80cc:	d9800717 	ldw	r6,28(sp)
        ldw   r7,  32(sp)
    80d0:	d9c00817 	ldw	r7,32(sp)

#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
        ldw   et, %gprel(alt_exception_old_stack_limit)(gp)
#endif

        ldw   r8,  36(sp)
    80d4:	da000917 	ldw	r8,36(sp)
        ldw   r9,  40(sp)
    80d8:	da400a17 	ldw	r9,40(sp)
        ldw   r10, 44(sp)
    80dc:	da800b17 	ldw	r10,44(sp)
        ldw   r11, 48(sp)
    80e0:	dac00c17 	ldw	r11,48(sp)
        ldw   r12, 52(sp)
    80e4:	db000d17 	ldw	r12,52(sp)
        ldw   r13, 56(sp)
    80e8:	db400e17 	ldw	r13,56(sp)
        ldw   r14, 60(sp)
    80ec:	db800f17 	ldw	r14,60(sp)
        ldw   r15, 64(sp)
    80f0:	dbc01017 	ldw	r15,64(sp)
        stw   et, %gprel(alt_stack_limit_value)(gp)
        stw   zero, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
        ldw   sp,  76(sp)
#else /* ALT_EXCEPTION_STACK disabled */
        addi  sp, sp, 76
    80f4:	dec01304 	addi	sp,sp,76

        /*
         * Return to the interrupted instruction.
         */

        eret
    80f8:	ef80083a 	eret

000080fc <alt_irq_handler>:
 * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined.
 */

void alt_irq_handler (void) __attribute__ ((section (".exceptions")));
void alt_irq_handler (void)
{
    80fc:	defffe04 	addi	sp,sp,-8
    8100:	dfc00115 	stw	ra,4(sp)
    8104:	dc000015 	stw	r16,0(sp)
#ifndef NIOS2_EIC_PRESENT
static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void)
{
  alt_u32 active;

  NIOS2_READ_IPENDING (active);
    8108:	0009313a 	rdctl	r4,ipending
    do
    {
      if (active & mask)
      { 
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
        alt_irq[i].handler(alt_irq[i].context); 
    810c:	04000074 	movhi	r16,1
    8110:	84214104 	addi	r16,r16,-31484

  active = alt_irq_pending ();

  do
  {
    i = 0;
    8114:	0005883a 	mov	r2,zero
    mask = 1;
    8118:	00c00044 	movi	r3,1
     * called to clear the interrupt condition.
     */

    do
    {
      if (active & mask)
    811c:	20ca703a 	and	r5,r4,r3
    8120:	28000b26 	beq	r5,zero,8150 <alt_irq_handler+0x54>
      { 
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
        alt_irq[i].handler(alt_irq[i].context); 
    8124:	100490fa 	slli	r2,r2,3
    8128:	8085883a 	add	r2,r16,r2
    812c:	10c00017 	ldw	r3,0(r2)
    8130:	11000117 	ldw	r4,4(r2)
    8134:	183ee83a 	callr	r3
    8138:	0009313a 	rdctl	r4,ipending

    } while (1);

    active = alt_irq_pending ();
    
  } while (active);
    813c:	203ff51e 	bne	r4,zero,8114 <_gp+0xffff7c30>
  /*
   * Notify the operating system that interrupt processing is complete.
   */ 

  ALT_OS_INT_EXIT();
}
    8140:	dfc00117 	ldw	ra,4(sp)
    8144:	dc000017 	ldw	r16,0(sp)
    8148:	dec00204 	addi	sp,sp,8
    814c:	f800283a 	ret
#else
        alt_irq[i].handler(alt_irq[i].context, i); 
#endif
        break;
      }
      mask <<= 1;
    8150:	18c7883a 	add	r3,r3,r3
      i++;
    8154:	10800044 	addi	r2,r2,1

    } while (1);
    8158:	003ff006 	br	811c <_gp+0xffff7c38>

0000815c <alt_instruction_exception_entry>:
#else
  cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT;
  badaddr = 0;
#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */

  if(alt_instruction_exception_handler) {
    815c:	d0a00717 	ldw	r2,-32740(gp)
    8160:	10000426 	beq	r2,zero,8174 <alt_instruction_exception_entry+0x18>
     * Call handler. Its return value indicates whether the exception-causing
     * instruction should be re-issued. The code that called us,
     * alt_eceptions_entry.S, will look at this value and adjust the ea
     * register as necessary
     */
    return alt_instruction_exception_handler(cause, exception_pc, badaddr);
    8164:	200b883a 	mov	r5,r4
    8168:	000d883a 	mov	r6,zero
    816c:	013fffc4 	movi	r4,-1
    8170:	1000683a 	jmp	r2
   *    (a peripheral which negates its interrupt output before its
   *    interrupt handler has been executed will cause spurious interrupts)
   */
  else {
#ifdef NIOS2_HAS_DEBUG_STUB
    NIOS2_BREAK();
    8174:	003da03a 	break	0
#endif /* NIOS2_HAS_DEBUG_STUB */
  }

  /* We should not get here. Remove compiler warning. */
  return NIOS2_EXCEPTION_RETURN_REISSUE_INST;
}
    8178:	0005883a 	mov	r2,zero
    817c:	f800283a 	ret

Disassembly of section .text:

00008180 <_start>:

    /*
     * Now that the caches are initialized, set up the stack pointer and global pointer.
     * The values provided by the linker are assumed to be correctly aligned.
     */
    movhi sp, %hi(__alt_stack_pointer)
    8180:	06c00074 	movhi	sp,1
    ori sp, sp, %lo(__alt_stack_pointer)
    8184:	dec00014 	ori	sp,sp,0
    movhi gp, %hi(_gp)
    8188:	06800074 	movhi	gp,1
    ori gp, gp, %lo(_gp)
    818c:	d6813914 	ori	gp,gp,1252
 */
#ifndef ALT_SIM_OPTIMIZE
    /* Log that the BSS is about to be cleared. */
    ALT_LOG_PUTS(alt_log_msg_bss)

    movhi r2, %hi(__bss_start)
    8190:	00800034 	movhi	r2,0
    ori r2, r2, %lo(__bss_start)
    8194:	10a13b14 	ori	r2,r2,34028

    movhi r3, %hi(__bss_end)
    8198:	00c00034 	movhi	r3,0
    ori r3, r3, %lo(__bss_end)
    819c:	18e18114 	ori	r3,r3,34308

    beq r2, r3, 1f
    81a0:	10c00326 	beq	r2,r3,81b0 <_start+0x30>

0:
    stw zero, (r2)
    81a4:	10000015 	stw	zero,0(r2)
    addi r2, r2, 4
    81a8:	10800104 	addi	r2,r2,4
    bltu r2, r3, 0b
    81ac:	10fffd36 	bltu	r2,r3,81a4 <_gp+0xffff7cc0>
     * section aren't defined until alt_load() has been called).
     */
    mov   et, zero
#endif

    call alt_load
    81b0:	00083300 	call	8330 <alt_load>

    /* Log that alt_main is about to be called. */
    ALT_LOG_PUTS(alt_log_msg_alt_main)

    /* Call the C entry point. It should never return. */
    call alt_main
    81b4:	00084100 	call	8410 <alt_main>

000081b8 <alt_after_alt_main>:

    /* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
    br alt_after_alt_main
    81b8:	003fff06 	br	81b8 <_gp+0xffff7cd4>

000081bc <irr>:
#include "altera_avalon_timer_regs.h"

volatile int counter = 0;

static void irr(){
	counter++;
    81bc:	d0a00217 	ldw	r2,-32760(gp)
    81c0:	10800044 	addi	r2,r2,1
    81c4:	d0a00215 	stw	r2,-32760(gp)
	IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, counter );
    81c8:	d0e00217 	ldw	r3,-32760(gp)
    81cc:	00800074 	movhi	r2,1
    81d0:	10840804 	addi	r2,r2,4128
    81d4:	10c00035 	stwio	r3,0(r2)
	IOWR_ALTERA_AVALON_TIMER_STATUS(TIMER_0_BASE, 0);
    81d8:	00800074 	movhi	r2,1
    81dc:	10840004 	addi	r2,r2,4096
    81e0:	10000035 	stwio	zero,0(r2)
    81e4:	f800283a 	ret

000081e8 <main>:
}

int main()
{ 
    81e8:	defffe04 	addi	sp,sp,-8
	/* TIMER */
	IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_0_BASE,
    81ec:	00800074 	movhi	r2,1
	IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, counter );
	IOWR_ALTERA_AVALON_TIMER_STATUS(TIMER_0_BASE, 0);
}

int main()
{ 
    81f0:	dfc00115 	stw	ra,4(sp)
	/* TIMER */
	IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_0_BASE,
    81f4:	10840104 	addi	r2,r2,4100
    81f8:	00c001c4 	movi	r3,7
    81fc:	10c00035 	stwio	r3,0(r2)
			ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
			ALTERA_AVALON_TIMER_CONTROL_ITO_MSK
			);

	/* IRQ */
	alt_ic_isr_register(TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID,TIMER_0_IRQ, irr, NULL, 0);
    8200:	01800074 	movhi	r6,1
    8204:	000b883a 	mov	r5,zero
    8208:	0009883a 	mov	r4,zero
    820c:	d8000015 	stw	zero,0(sp)
    8210:	000f883a 	mov	r7,zero
    8214:	31a06f04 	addi	r6,r6,-32324
    8218:	000822c0 	call	822c <alt_ic_isr_register>
	alt_ic_irq_enable(0,0);
    821c:	000b883a 	mov	r5,zero
    8220:	0009883a 	mov	r4,zero
    8224:	00082300 	call	8230 <alt_ic_irq_enable>
    8228:	003fff06 	br	8228 <_gp+0xffff7d44>

0000822c <alt_ic_isr_register>:
  * @return                 0 if successful, else error (-1)
  */
int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
  void *isr_context, void *flags)
{
    return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags);
    822c:	00082c81 	jmpi	82c8 <alt_iic_isr_register>

00008230 <alt_ic_irq_enable>:
static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
       alt_irq_disable_all (void)
{
  alt_irq_context context;

  NIOS2_READ_STATUS (context);
    8230:	000d303a 	rdctl	r6,status

  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
    8234:	00bfff84 	movi	r2,-2
    8238:	3084703a 	and	r2,r6,r2
    823c:	1001703a 	wrctl	status,r2
  alt_irq_context  status;
  extern volatile alt_u32 alt_irq_active;

  status = alt_irq_disable_all ();

  alt_irq_active |= (1 << id);
    8240:	00800074 	movhi	r2,1
    8244:	10a13c04 	addi	r2,r2,-31504
    8248:	01000044 	movi	r4,1
    824c:	10c00017 	ldw	r3,0(r2)
    8250:	214a983a 	sll	r5,r4,r5
    8254:	28cab03a 	or	r5,r5,r3
    8258:	11400015 	stw	r5,0(r2)
  NIOS2_WRITE_IENABLE (alt_irq_active);
    825c:	10800017 	ldw	r2,0(r2)
    8260:	100170fa 	wrctl	ienable,r2
  status &= ~NIOS2_STATUS_PIE_MSK;
  status |= (context & NIOS2_STATUS_PIE_MSK);
  
  NIOS2_WRITE_STATUS (status);
#else
  NIOS2_WRITE_STATUS (context);
    8264:	3001703a 	wrctl	status,r6
  * @return                 0 if successful, else error (-1)
  */
int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq)
{
    return alt_irq_enable(irq);
}
    8268:	0005883a 	mov	r2,zero
    826c:	f800283a 	ret

00008270 <alt_ic_irq_disable>:
static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
       alt_irq_disable_all (void)
{
  alt_irq_context context;

  NIOS2_READ_STATUS (context);
    8270:	000d303a 	rdctl	r6,status

  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
    8274:	00bfff84 	movi	r2,-2
    8278:	3084703a 	and	r2,r6,r2
    827c:	1001703a 	wrctl	status,r2
  alt_irq_context  status;
  extern volatile alt_u32 alt_irq_active;

  status = alt_irq_disable_all ();

  alt_irq_active &= ~(1 << id);
    8280:	00800074 	movhi	r2,1
    8284:	10a13c04 	addi	r2,r2,-31504
    8288:	013fff84 	movi	r4,-2
    828c:	10c00017 	ldw	r3,0(r2)
    8290:	214a183a 	rol	r5,r4,r5
    8294:	28ca703a 	and	r5,r5,r3
    8298:	11400015 	stw	r5,0(r2)
  NIOS2_WRITE_IENABLE (alt_irq_active);
    829c:	10800017 	ldw	r2,0(r2)
    82a0:	100170fa 	wrctl	ienable,r2
  status &= ~NIOS2_STATUS_PIE_MSK;
  status |= (context & NIOS2_STATUS_PIE_MSK);
  
  NIOS2_WRITE_STATUS (status);
#else
  NIOS2_WRITE_STATUS (context);
    82a4:	3001703a 	wrctl	status,r6
  * @return                 0 if successful, else error (-1)
  */
int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq)
{
    return alt_irq_disable(irq);
}
    82a8:	0005883a 	mov	r2,zero
    82ac:	f800283a 	ret

000082b0 <alt_ic_irq_enabled>:
  */
alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq)
{
    alt_u32 irq_enabled;

    NIOS2_READ_IENABLE(irq_enabled);
    82b0:	000730fa 	rdctl	r3,ienable

    return (irq_enabled & (1 << irq)) ? 1: 0;
    82b4:	00800044 	movi	r2,1
    82b8:	1144983a 	sll	r2,r2,r5
    82bc:	10c4703a 	and	r2,r2,r3
}
    82c0:	1004c03a 	cmpne	r2,r2,zero
    82c4:	f800283a 	ret

000082c8 <alt_iic_isr_register>:
{
  int rc = -EINVAL;  
  int id = irq;             /* IRQ interpreted as the interrupt ID. */
  alt_irq_context status;

  if (id < ALT_NIRQ)
    82c8:	00c007c4 	movi	r3,31
    82cc:	19401616 	blt	r3,r5,8328 <alt_iic_isr_register+0x60>
  * @param flags            
  * @return                 0 if successful, else error (-1)
  */
int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
  void *isr_context, void *flags)
{
    82d0:	defffe04 	addi	sp,sp,-8
    82d4:	dfc00115 	stw	ra,4(sp)
    82d8:	dc000015 	stw	r16,0(sp)
static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
       alt_irq_disable_all (void)
{
  alt_irq_context context;

  NIOS2_READ_STATUS (context);
    82dc:	0021303a 	rdctl	r16,status

  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
    82e0:	00ffff84 	movi	r3,-2
    82e4:	80c6703a 	and	r3,r16,r3
    82e8:	1801703a 	wrctl	status,r3
     * state.
     */

    status = alt_irq_disable_all();

    alt_irq[id].handler = isr;
    82ec:	280490fa 	slli	r2,r5,3
    82f0:	00c00074 	movhi	r3,1
    82f4:	18e14104 	addi	r3,r3,-31484
    82f8:	1885883a 	add	r2,r3,r2
    82fc:	11800015 	stw	r6,0(r2)
    alt_irq[id].context = isr_context;
    8300:	11c00115 	stw	r7,4(r2)

    rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id);
    8304:	30000226 	beq	r6,zero,8310 <alt_iic_isr_register+0x48>
    8308:	00082300 	call	8230 <alt_ic_irq_enable>
    830c:	00000106 	br	8314 <alt_iic_isr_register+0x4c>
    8310:	00082700 	call	8270 <alt_ic_irq_disable>
  status &= ~NIOS2_STATUS_PIE_MSK;
  status |= (context & NIOS2_STATUS_PIE_MSK);
  
  NIOS2_WRITE_STATUS (status);
#else
  NIOS2_WRITE_STATUS (context);
    8314:	8001703a 	wrctl	status,r16

    alt_irq_enable_all(status);
  }

  return rc; 
}
    8318:	dfc00117 	ldw	ra,4(sp)
    831c:	dc000017 	ldw	r16,0(sp)
    8320:	dec00204 	addi	sp,sp,8
    8324:	f800283a 	ret
  * @return                 0 if successful, else error (-1)
  */
int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
  void *isr_context, void *flags)
{
  int rc = -EINVAL;  
    8328:	00bffa84 	movi	r2,-22
    832c:	f800283a 	ret

00008330 <alt_load>:
 * there is no bootloader, so this application is responsible for loading to
 * RAM any sections that are required.
 */  

void alt_load (void)
{
    8330:	deffff04 	addi	sp,sp,-4
    8334:	01000074 	movhi	r4,1
    8338:	01400074 	movhi	r5,1
    833c:	dfc00015 	stw	ra,0(sp)
    8340:	21213904 	addi	r4,r4,-31516
    8344:	29613a04 	addi	r5,r5,-31512

static void ALT_INLINE alt_load_section (alt_u32* from, 
                                         alt_u32* to, 
                                         alt_u32* end)
{
  if (to != from)
    8348:	2140061e 	bne	r4,r5,8364 <alt_load+0x34>
    834c:	01000074 	movhi	r4,1
    8350:	01400074 	movhi	r5,1
    8354:	21200804 	addi	r4,r4,-32736
    8358:	29600804 	addi	r5,r5,-32736
    835c:	2140121e 	bne	r4,r5,83a8 <alt_load+0x78>
    8360:	00000b06 	br	8390 <alt_load+0x60>
    8364:	00c00074 	movhi	r3,1
    8368:	18e13a04 	addi	r3,r3,-31512
    836c:	1907c83a 	sub	r3,r3,r4
    8370:	0005883a 	mov	r2,zero
  {
    while( to != end )
    8374:	10fff526 	beq	r2,r3,834c <_gp+0xffff7e68>
    {
      *to++ = *from++;
    8378:	114f883a 	add	r7,r2,r5
    837c:	39c00017 	ldw	r7,0(r7)
    8380:	110d883a 	add	r6,r2,r4
    8384:	10800104 	addi	r2,r2,4
    8388:	31c00015 	stw	r7,0(r6)
    838c:	003ff906 	br	8374 <_gp+0xffff7e90>
    8390:	01000074 	movhi	r4,1
    8394:	01400074 	movhi	r5,1
    8398:	21213904 	addi	r4,r4,-31516
    839c:	29613904 	addi	r5,r5,-31516

static void ALT_INLINE alt_load_section (alt_u32* from, 
                                         alt_u32* to, 
                                         alt_u32* end)
{
  if (to != from)
    83a0:	2140101e 	bne	r4,r5,83e4 <alt_load+0xb4>
    83a4:	00000b06 	br	83d4 <alt_load+0xa4>
    83a8:	00c00074 	movhi	r3,1
    83ac:	18e06004 	addi	r3,r3,-32384
    83b0:	1907c83a 	sub	r3,r3,r4
    83b4:	0005883a 	mov	r2,zero
  {
    while( to != end )
    83b8:	10fff526 	beq	r2,r3,8390 <_gp+0xffff7eac>
    {
      *to++ = *from++;
    83bc:	114f883a 	add	r7,r2,r5
    83c0:	39c00017 	ldw	r7,0(r7)
    83c4:	110d883a 	add	r6,r2,r4
    83c8:	10800104 	addi	r2,r2,4
    83cc:	31c00015 	stw	r7,0(r6)
    83d0:	003ff906 	br	83b8 <_gp+0xffff7ed4>
  
  /*
   * Now ensure that the caches are in synch.
   */
  
  alt_dcache_flush_all();
    83d4:	00084600 	call	8460 <alt_dcache_flush_all>
  alt_icache_flush_all();
}
    83d8:	dfc00017 	ldw	ra,0(sp)
    83dc:	dec00104 	addi	sp,sp,4
  /*
   * Now ensure that the caches are in synch.
   */
  
  alt_dcache_flush_all();
  alt_icache_flush_all();
    83e0:	00084641 	jmpi	8464 <alt_icache_flush_all>
    83e4:	00c00074 	movhi	r3,1
    83e8:	18e13904 	addi	r3,r3,-31516
    83ec:	1907c83a 	sub	r3,r3,r4

static void ALT_INLINE alt_load_section (alt_u32* from, 
                                         alt_u32* to, 
                                         alt_u32* end)
{
  if (to != from)
    83f0:	0005883a 	mov	r2,zero
  {
    while( to != end )
    83f4:	18bff726 	beq	r3,r2,83d4 <_gp+0xffff7ef0>
    {
      *to++ = *from++;
    83f8:	114f883a 	add	r7,r2,r5
    83fc:	39c00017 	ldw	r7,0(r7)
    8400:	110d883a 	add	r6,r2,r4
    8404:	10800104 	addi	r2,r2,4
    8408:	31c00015 	stw	r7,0(r6)
    840c:	003ff906 	br	83f4 <_gp+0xffff7f10>

00008410 <alt_main>:
 * devices/filesystems/components in the system; and call the entry point for
 * the users application, i.e. main().
 */

void alt_main (void)
{
    8410:	deffff04 	addi	sp,sp,-4
#endif

  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
  /* Initialize the interrupt controller. */
  alt_irq_init (NULL);
    8414:	0009883a 	mov	r4,zero
 * devices/filesystems/components in the system; and call the entry point for
 * the users application, i.e. main().
 */

void alt_main (void)
{
    8418:	dfc00015 	stw	ra,0(sp)
#endif

  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
  /* Initialize the interrupt controller. */
  alt_irq_init (NULL);
    841c:	000843c0 	call	843c <alt_irq_init>
  ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n");
  ALT_SEM_CREATE (&alt_fd_list_lock, 1);

  /* Initialize the device drivers/software components. */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n");
  alt_sys_init();
    8420:	000845c0 	call	845c <alt_sys_init>
   */

  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");

#ifdef ALT_NO_EXIT
  main (alt_argc, alt_argv, alt_envp);
    8424:	d1a00417 	ldw	r6,-32752(gp)
    8428:	d1600517 	ldw	r5,-32748(gp)
    842c:	d1200617 	ldw	r4,-32744(gp)
  close(STDOUT_FILENO);
  exit (result);
#endif

  ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n");
}
    8430:	dfc00017 	ldw	ra,0(sp)
    8434:	dec00104 	addi	sp,sp,4
   */

  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");

#ifdef ALT_NO_EXIT
  main (alt_argc, alt_argv, alt_envp);
    8438:	00081e81 	jmpi	81e8 <main>

0000843c <alt_irq_init>:
 * The "base" parameter is ignored and only
 * present for backwards-compatibility.
 */

void alt_irq_init ( const void* base )
{
    843c:	deffff04 	addi	sp,sp,-4
    8440:	dfc00015 	stw	ra,0(sp)
    ALTERA_NIOS2_GEN2_IRQ_INIT ( NIOS2_GEN2_0, nios2_gen2_0);
    8444:	00084dc0 	call	84dc <altera_nios2_gen2_irq_init>
 * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts.
 */
static ALT_INLINE void ALT_ALWAYS_INLINE 
       alt_irq_cpu_enable_interrupts (void)
{
    NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK
    8448:	00800044 	movi	r2,1
    844c:	1001703a 	wrctl	status,r2
    alt_irq_cpu_enable_interrupts();
}
    8450:	dfc00017 	ldw	ra,0(sp)
    8454:	dec00104 	addi	sp,sp,4
    8458:	f800283a 	ret

0000845c <alt_sys_init>:
 * Initialize the non-interrupt controller devices.
 * Called after alt_irq_init().
 */

void alt_sys_init( void )
{
    845c:	f800283a 	ret

00008460 <alt_dcache_flush_all>:
/*
 * alt_dcache_flush_all() is called to flush the entire data cache.
 */

void alt_dcache_flush_all (void)
{
    8460:	f800283a 	ret

00008464 <alt_icache_flush_all>:
/*
 * alt_icache_flush_all() is called to flush the entire instruction cache.
 */

void alt_icache_flush_all (void)
{
    8464:	f800283a 	ret

00008468 <alt_exception_cause_generated_bad_addr>:
 *         0: BADADDR is not valid
 */
int 
alt_exception_cause_generated_bad_addr(alt_exception_cause cause)
{
  switch (cause) {
    8468:	213ffe84 	addi	r4,r4,-6
    846c:	008003c4 	movi	r2,15
    8470:	11001636 	bltu	r2,r4,84cc <alt_exception_cause_generated_bad_addr+0x64>
    8474:	200890ba 	slli	r4,r4,2
    8478:	00800074 	movhi	r2,1
    847c:	10a12304 	addi	r2,r2,-31604
    8480:	2089883a 	add	r4,r4,r2
    8484:	20800017 	ldw	r2,0(r4)
    8488:	1000683a 	jmp	r2
    848c:	000084d4 	movui	zero,531
    8490:	000084d4 	movui	zero,531
    8494:	000084cc 	andi	zero,zero,531
    8498:	000084cc 	andi	zero,zero,531
    849c:	000084cc 	andi	zero,zero,531
    84a0:	000084d4 	movui	zero,531
    84a4:	000084cc 	andi	zero,zero,531
    84a8:	000084cc 	andi	zero,zero,531
    84ac:	000084d4 	movui	zero,531
    84b0:	000084d4 	movui	zero,531
    84b4:	000084cc 	andi	zero,zero,531
    84b8:	000084d4 	movui	zero,531
    84bc:	000084cc 	andi	zero,zero,531
    84c0:	000084cc 	andi	zero,zero,531
    84c4:	000084cc 	andi	zero,zero,531
    84c8:	000084d4 	movui	zero,531
  case NIOS2_EXCEPTION_ECC_DATA_ERR:
    return 1;

  case NIOS2_EXCEPTION_TLB_MISS:
  case NIOS2_EXCEPTION_ECC_TLB_ERR:
    return 0;
    84cc:	0005883a 	mov	r2,zero
    84d0:	f800283a 	ret
  case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC:
  case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION:
  case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION:
  case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION:
  case NIOS2_EXCEPTION_ECC_DATA_ERR:
    return 1;
    84d4:	00800044 	movi	r2,1
    return 0;

  default:
    return 0;
  }
}
    84d8:	f800283a 	ret

000084dc <altera_nios2_gen2_irq_init>:
 * To initialize the internal interrupt controller, just clear the IENABLE
 * register so that all possible IRQs are disabled.
 */
void altera_nios2_gen2_irq_init(void) 
{
    NIOS2_WRITE_IENABLE(0);
    84dc:	000170fa 	wrctl	ienable,zero
    84e0:	f800283a 	ret
