{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1475006832680 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1475006832680 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "NIOS_LED 10M08DAF256C8GES " "Selected device 10M08DAF256C8GES for design \"NIOS_LED\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1475006832713 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1475006832787 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1475006832787 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1475006833018 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1475006833028 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF256C8G " "Device 10M08DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1475006833516 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04DAF256C8G " "Device 10M04DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1475006833516 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF256C8G " "Device 10M16DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1475006833516 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF256C8G " "Device 10M25DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1475006833516 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF256C8GES " "Device 10M50DAF256C8GES is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1475006833516 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF256C8G " "Device 10M50DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1475006833516 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF256C8G " "Device 10M40DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1475006833516 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1475006833516 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ F8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location F8" {  } { { "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 5610 14046 14942 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1475006833525 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" {  } { { "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 5612 14046 14942 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1475006833525 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ F7 " "Pin ~ALTERA_nSTATUS~ is reserved at location F7" {  } { { "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 5614 14046 14942 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1475006833525 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E7 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E7" {  } { { "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 5616 14046 14942 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1475006833525 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1475006833525 ""}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" {  } {  } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1475006833526 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1475006833526 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1475006833526 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1475006833526 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1475006833527 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1475006833561 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1475006834732 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1475006834732 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1475006834732 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1475006834732 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1475006834732 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1475006834732 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/altera_reset_controller.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1475006834748 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1475006834756 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|monitor_ready clk_clk " "Register NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|monitor_ready is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1475006834785 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1475006834785 "|NIOS_LED|clk_clk"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1475006834786 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1475006834786 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1475006834807 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1475006834807 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1475006834807 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1475006834807 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1475006834808 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1475006834808 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1475006834808 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1475006834808 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_clk~input (placed in PIN L3 (CLK0p, DIFFIO_RX_L18p, DIFFOUT_L18p, High_Speed)) " "Automatically promoted node clk_clk~input (placed in PIN L3 (CLK0p, DIFFIO_RX_L18p, DIFFOUT_L18p, High_Speed))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1475006835061 ""}  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 11 0 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 5599 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1475006835061 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1475006835061 ""}  } { { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 5249 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1475006835061 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_reset_controller:rst_controller\|r_sync_rst  " "Automatically promoted node altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1475006835061 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node altera_reset_controller:rst_controller\|WideOr0~0" {  } { { "NIOS_LED/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_controller.v" 290 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 2080 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1475006835061 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|W_rf_wren " "Destination node NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|W_rf_wren" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 3440 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1616 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1475006835061 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1 " "Destination node NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1" {  } { { "altera_std_synchronizer.v" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1" } } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 863 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1475006835061 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1475006835061 ""}  } { { "NIOS_LED/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_controller.v" 288 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 174 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1475006835061 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|resetrequest  " "Automatically promoted node NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|resetrequest " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1475006835062 ""}  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 184 -1 0 } } { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|resetrequest" } } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 868 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1475006835062 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1475006835730 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1475006835734 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1475006835734 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1475006835740 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1475006835747 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1475006835755 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1475006835755 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1475006835759 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1475006835824 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1475006835829 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1475006835829 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1475006835916 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1475006835924 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1475006836818 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1475006837182 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1475006837226 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1475006837905 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1475006837905 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1475006838766 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "7 " "Router estimated average interconnect usage is 7% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X21_Y13 X31_Y25 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y13 to location X31_Y25" {  } { { "loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X21_Y13 to location X31_Y25"} { { 12 { 0 ""} 21 13 11 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1475006839949 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1475006839949 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1475006840220 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1475006840220 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1475006840220 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1475006840224 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.34 " "Total time spent on timing analysis during the Fitter is 0.34 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1475006840515 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1475006840541 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M08DAF256C8GES " "Timing characteristics of device 10M08DAF256C8GES are preliminary" {  } {  } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1475006840541 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1475006841663 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1475006841664 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M08DAF256C8GES " "Timing characteristics of device 10M08DAF256C8GES are preliminary" {  } {  } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1475006841664 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1475006843067 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1475006844045 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/ALTERA/NIOS_LED/output_files/NIOS_LED.fit.smsg " "Generated suppressed messages file C:/ALTERA/NIOS_LED/output_files/NIOS_LED.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1475006844555 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 9 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1740 " "Peak virtual memory: 1740 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1475006845802 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 27 22:07:25 2016 " "Processing ended: Tue Sep 27 22:07:25 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1475006845802 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1475006845802 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1475006845802 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1475006845802 ""}
