Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
trigger_module 2 0 0 0 11 0 0 0 0 0 0 0 0
RAM_DISP|altsyncram_component|auto_generated 32 0 0 0 9 0 0 0 0 0 0 0 0
RAM_DISP 32 0 0 0 9 0 0 0 0 0 0 0 0
LINE1 41 21 0 21 4 21 21 21 0 0 0 0 0
VGA1 5 1 0 1 26 1 1 1 0 0 0 0 0
adc_command1 21 12 7 12 21 12 12 12 0 0 0 0 0
u0|adc|control_internal|adc_inst|adcblock_instance 9 0 0 0 14 0 0 0 0 0 0 0 0
u0|adc|control_internal|adc_inst|decoder 5 0 0 0 5 0 0 0 0 0 0 0 0
u0|adc|control_internal|adc_inst 9 0 0 0 14 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram 28 0 0 0 12 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state 5 0 0 0 2 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo 16 0 0 0 14 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated 16 0 0 0 14 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo 16 0 0 0 12 0 0 0 0 0 0 0 0
u0|adc|control_internal|u_control_fsm 26 0 0 0 30 0 0 0 0 0 0 0 0
u0|adc|control_internal 13 1 0 1 21 1 1 1 0 0 0 0 0
u0|adc 12 0 0 0 21 0 0 0 0 0 0 0 0
u0 12 2 0 2 21 2 2 2 0 0 0 0 0
pll1|altpll_component|auto_generated 2 0 0 0 6 0 0 0 0 0 0 0 0
pll1 1 1 0 1 5 1 1 1 0 0 0 0 0