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modular_adc_0

altera_modular_adc v15.1

Parameters CORE_VAR 3 ENABLE_DEBUG 0 MONITOR_COUNT_WIDTH 12 CLOCK_FREQ 0 FAMILY MAX10FPGA DEVICE_PART 10M08DAF256C8GES device_partname_fivechar_prefix 10M08 device_adc_type 12 max_adc_count_on_die 1 adc_count_on_device 1 device_power_supply_type 2 ip_is_for_which_adc 1 is_this_first_or_second_adc 1 analog_input_pin_mask 0 hard_pwd 0 clkdiv 2 tsclkdiv 1 tsclksel 1 refsel 0 external_vref 2.5 int_vref_vr 3.0 int_vref_nonvr 2.5 reference_voltage 2.5 prescalar 0 use_tsd false en_tsd_max false tsd_max 125 en_tsd_min false tsd_min 0 use_ch0 true en_thmax_ch0 false thmax_ch0 0.0 en_thmin_ch0 false thmin_ch0 0.0 use_ch1 false en_thmax_ch1 false thmax_ch1 0.0 en_thmin_ch1 false thmin_ch1 0.0 use_ch2 false en_thmax_ch2 false thmax_ch2 0.0 en_thmin_ch2 false thmin_ch2 0.0 use_ch3 false en_thmax_ch3 false thmax_ch3 0.0 en_thmin_ch3 false thmin_ch3 0.0 use_ch4 false en_thmax_ch4 false thmax_ch4 0.0 en_thmin_ch4 false thmin_ch4 0.0 use_ch5 false en_thmax_ch5 false thmax_ch5 0.0 en_thmin_ch5 false thmin_ch5 0.0 use_ch6 false en_thmax_ch6 false thmax_ch6 0.0 en_thmin_ch6 false thmin_ch6 0.0 use_ch7 false en_thmax_ch7 false thmax_ch7 0.0 en_thmin_ch7 false thmin_ch7 0.0 use_ch8 false prescaler_ch8 false en_thmax_ch8 false thmax_ch8 0.0 en_thmin_ch8 false thmin_ch8 0.0 use_ch9 false en_thmax_ch9 false thmax_ch9 0.0 en_thmin_ch9 false thmin_ch9 0.0 use_ch10 false en_thmax_ch10 false thmax_ch10 0.0 en_thmin_ch10 false thmin_ch10 0.0 use_ch11 false en_thmax_ch11 false thmax_ch11 0.0 en_thmin_ch11 false thmin_ch11 0.0 use_ch12 false en_thmax_ch12 false thmax_ch12 0.0 en_thmin_ch12 false thmin_ch12 0.0 use_ch13 false en_thmax_ch13 false thmax_ch13 0.0 en_thmin_ch13 false thmin_ch13 0.0 use_ch14 false en_thmax_ch14 false thmax_ch14 0.0 en_thmin_ch14 false thmin_ch14 0.0 use_ch15 false en_thmax_ch15 false thmax_ch15 0.0 en_thmin_ch15 false thmin_ch15 0.0 use_ch16 false prescaler_ch16 false en_thmax_ch16 false thmax_ch16 0.0 en_thmin_ch16 false thmin_ch16 0.0 seq_order_length 1 seq_order_slot_1 30 seq_order_slot_2 30 seq_order_slot_3 30 seq_order_slot_4 30 seq_order_slot_5 30 seq_order_slot_6 30 seq_order_slot_7 30 seq_order_slot_8 30 seq_order_slot_9 30 seq_order_slot_10 30 seq_order_slot_11 30 seq_order_slot_12 30 seq_order_slot_13 30 seq_order_slot_14 30 seq_order_slot_15 30 seq_order_slot_16 30 seq_order_slot_17 30 seq_order_slot_18 30 seq_order_slot_19 30 seq_order_slot_20 30 seq_order_slot_21 30 seq_order_slot_22 30 seq_order_slot_23 30 seq_order_slot_24 30 seq_order_slot_25 30 seq_order_slot_26 30 seq_order_slot_27 30 seq_order_slot_28 30 seq_order_slot_29 30 seq_order_slot_30 30 seq_order_slot_31 30 seq_order_slot_32 30 seq_order_slot_33 30 seq_order_slot_34 30 seq_order_slot_35 30 seq_order_slot_36 30 seq_order_slot_37 30 seq_order_slot_38 30 seq_order_slot_39 30 seq_order_slot_40 30 seq_order_slot_41 30 seq_order_slot_42 30 seq_order_slot_43 30 seq_order_slot_44 30 seq_order_slot_45 30 seq_order_slot_46 30 seq_order_slot_47 30 seq_order_slot_48 30 seq_order_slot_49 30 seq_order_slot_50 30 seq_order_slot_51 30 seq_order_slot_52 30 seq_order_slot_53 30 seq_order_slot_54 30 seq_order_slot_55 30 seq_order_slot_56 30 seq_order_slot_57 30 seq_order_slot_58 30 seq_order_slot_59 30 seq_order_slot_60 30 seq_order_slot_61 30 seq_order_slot_62 30 seq_order_slot_63 30 seq_order_slot_64 30 AUTO_DEVICE_SPEEDGRADE 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CORE_VARIANT 3 DUAL_ADC_MODE false PRESCALER_CH16 0 PRESCALER_CH8 0 REFSEL External VREF USE_CH0 1 USE_CH1 0 USE_CH10 0 USE_CH11 0 USE_CH12 0 USE_CH13 0 USE_CH14 0 USE_CH15 0 USE_CH16 0 USE_CH2 0 USE_CH3 0 USE_CH4 0 USE_CH5 0 USE_CH6 0 USE_CH7 0 USE_CH8 0 USE_CH9 0 USE_TSD 0 VREF 2.5